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| nju6676 preliminary 64-common x 132-segment plus 1-icon bit map type lcd controller and driver general description package the nju6676 is a bit map lcd driver to display graphics or characters. it contains 8,580 bits display data ram, microprocessor interface circuits, instruction decoder, 132-segment drivers, 64-common drivers and 1- icon drivers. the bit image display data is transferred to the display data ram by serial or 8-bit parallel interface. 65 x 132 dots graphics or 8-character 4-line by 16 x 16 dots character with icon are displayed by nju6676 itself. the wide operating voltage from 2.2 to 5.5v and low operating current are useful for small size battery operating items. the build-in electrical variable resistance is very precision, furtheremore the rectangle outlook is very applicable to cog or slim tcp. features direct correspondence between display data ram and lcd pixel display data ram - 8,580 bits 197 lcd drivers - 65-common and 132-segment direct microprocessor interface for both of 68 and 80 type mpu serial interface programmable bias selection ; 1/7,1/9 bias useful instruction set display data read/write, display on/off cont, static indicator, display start line set, bias select, inverse display, common driver order assignment, power control set, page address set, column address set,status read, all on/off, adc select, read modify write, power saving. power supply circuits for lcd incorporated voltage booster circuits (4-time maximum), regulator, voltage follower x 4 precision electrical variable resistance (64-step) low power consumption 80ua(typ.). operating voltage (all the voltages are based on vdd=0v.) - rogic operating voltage : -2.2v -5.5v - voltage booster operating voltage : -2.5v - lcd driving voltage : -6.0v -18.0v rectangle outlook for cog package outline : bump-chip / tcp c-mos technology ver.1.31 NJU6676CH
nju6676 preliminary pad location fr osc2 vss2 vdd rd d0 d2 d1 d3 d5 d4 d6(scl) vdd d7(si) vdd vdd vdd vss vss vss vss2 vss2 vss2 vout c3- vout c3- c1+ c1+ c1- c2- c1- c2- c2+ c2+ vss vdd vss vdd v1 v1 v2 v3 v2 v3 v4 v4 v5 vr v5 vr vdd vdd vdd cls m/s vss p/s c86 vdd vdd vss y x s130 s131 s1 s0 c31 c30 comm c0 vss dof cs1 vdd cs2 res vss a0 wr frs cl osc1 dummy4 dummy2 dummy3 dummy1 comm c63 c32 c33 chip center : x=0um, y=0um chip size :x=8.72mm,y=2.37mm chip thickness : 675um 30um bump size : 45um x 83um pad pitch : 60um(min.) bump height : 15um(typ.) bump material : au nju6676 preliminary n pad coordinates chip size 8.72 x 2.37mm(chip center x=0um, y=0um) pad no. terminal x(um) y(um) pad no. terminal x(um) y(um) 1 dummy1 - 4139 - 1025 51 vdd 1655 - 1025 2 osc1 - 3347 - 1025 52 vdd 1715 - 1025 3 osc2 - 3287 - 1025 53 v1 1775 - 1025 4 frs - 3129 - 1025 54 v1 1835 - 1025 5 fr - 2909 - 1025 55 v2 1895 - 1025 6 cl - 2688 - 1025 56 v2 1955 - 1025 7 dof - 2468 - 1025 57 v3 2015 - 1025 8 vss - 2311 - 1025 58 v3 2075 - 1025 9 cs1 - 2251 - 1025 59 v4 2135 - 1025 10 cs2 - 2191 - 1025 60 v4 2195 - 10 25 11 vdd - 2131 - 1025 61 v5 2255 - 1025 12 res - 2071 - 1025 62 v5 2315 - 1025 13 a0 - 2011 - 1025 63 vr 2375 - 1025 14 vss - 1951 - 1025 64 vr 2435 - 1025 15 wr - 1891 - 1025 65 vdd 2495 - 1025 16 rd - 1831 - 1025 66 vdd 2555 - 1025 17 vdd - 1771 - 1025 67 vdd 2615 - 1025 18 d0 - 1613 - 1025 68 m/s 2675 - 1025 19 d1 - 1393 - 1025 69 cls 2810 - 1025 20 d2 - 1172 - 1025 70 vss 2870 - 1025 21 d3 - 952 - 1025 71 c86 2930 - 1025 22 d4 - 731 - 1025 72 p/s 3065 - 1025 23 d5 - 511 - 1025 73 vdd 3125 - 1025 24 d6(scl) - 29 1 - 1025 74 vss 3185 - 1025 25 d7(si) - 70 - 1025 75 vdd 3245 - 1025 26 vdd 155 - 1025 76 dummy2 4139 - 1025 27 vdd 215 - 1025 77 c31 4200 - 935 28 vdd 275 - 1025 78 c30 4200 - 875 29 vdd 335 - 1025 79 c29 4200 - 815 30 vss 395 - 1025 80 c28 4200 - 755 31 v ss 455 - 1025 81 c27 4200 - 695 32 vss 515 - 1025 82 c26 4200 - 635 33 vss2 575 - 1025 83 c25 4200 - 575 34 vss2 635 - 1025 84 c24 4200 - 515 35 vss2 695 - 1025 85 c23 4200 - 455 36 vss2 755 - 1025 86 c22 4200 - 395 37 vout 815 - 1025 87 c21 4200 - 335 38 vout 875 - 1025 88 c20 4200 - 275 39 c3 - 935 - 1025 89 c19 4200 - 215 40 c3 - 995 - 1025 90 c18 4200 - 155 41 c1 + 1055 - 1025 91 c17 4200 - 95 42 c1 + 1115 - 1025 92 c16 4200 - 35 43 c1 - 1175 - 1025 93 c15 4200 25 44 c1 - 1235 - 1025 94 c14 4200 85 45 c2 - 1 295 - 1025 95 c13 4200 145 46 c2 - 1355 - 1025 96 c12 4200 205 47 c2 + 1415 - 1025 97 c11 4200 265 48 c2 + 1475 - 1025 98 c10 4200 325 49 vss 1535 - 1025 99 c9 4200 385 50 vss 1595 - 1025 100 c8 4200 445 nju6676 preliminary pad no. terminal x(um) y(um) pad no. termin al x(um) y(um) 101 c7 4200 505 151 s40 1533 1025 102 c6 4200 565 152 s41 1473 1025 103 c5 4200 625 153 s42 1413 1025 104 c4 4200 685 154 s43 1353 1025 105 c3 4200 745 155 s44 1293 1025 106 c2 4200 805 156 s45 1233 1025 107 c1 4200 865 157 s46 1173 1025 108 c0 4200 925 158 s47 1113 1025 109 comm 4200 985 159 s48 1053 1025 110 dummy3 4119 1025 160 s49 993 1025 111 s0 3933 1025 161 s50 933 1025 112 s1 3873 1025 162 s51 873 1025 113 s2 3813 1025 163 s52 813 1025 114 s3 3753 1025 164 s53 753 1025 115 s4 3693 1025 165 s54 693 1025 116 s5 3633 1025 166 s55 633 1025 117 s6 3573 1025 167 s56 573 1025 118 s7 3513 1025 168 s57 513 1025 119 s8 3453 1025 169 s58 453 1025 120 s9 3393 1025 170 s59 393 1025 121 s10 3333 1025 171 s60 333 1025 122 s11 3273 1025 172 s61 273 1025 123 s12 3213 1025 173 s62 213 1025 124 s13 3153 1025 174 s63 153 1025 125 s14 3093 1025 175 s64 93 1025 126 s15 3033 1025 176 s65 33 1025 127 s16 2973 1025 177 s66 - 27 1025 128 s17 2913 1025 178 s6 7 - 87 1025 129 s18 2853 1025 179 s68 - 147 1025 130 s19 2793 1025 180 s69 - 207 1025 131 s20 2733 1025 181 s70 - 267 1025 132 s21 2673 1025 182 s71 - 327 1025 133 s22 2613 1025 183 s72 - 387 1025 134 s23 2553 1025 184 s73 - 447 1025 135 s24 2493 102 5 185 s74 - 507 1025 136 s25 2433 1025 186 s75 - 567 1025 137 s26 2373 1025 187 s76 - 627 1025 138 s27 2313 1025 188 s77 - 687 1025 139 s28 2253 1025 189 s78 - 747 1025 140 s29 2193 1025 190 s79 - 807 1025 141 s30 2133 1025 191 s80 - 867 1025 142 s3 1 2073 1025 192 s81 - 927 1025 143 s32 2013 1025 193 s82 - 987 1025 144 s33 1953 1025 194 s83 - 1047 1025 145 s34 1893 1025 195 s84 - 1107 1025 146 s35 1833 1025 196 s85 - 1167 1025 147 s36 1773 1025 197 s86 - 1227 1025 148 s37 1713 1025 198 s87 - 12 87 1025 149 s38 1653 1025 199 s88 - 1347 1025 150 s39 1593 1025 200 s89 - 1407 1025 nju6676 preliminary pad no. terminal x(um) y(um) pad no. terminal x(um) y(um) 201 s90 - 1467 1025 251 c39 - 4200 565 202 s91 - 1527 1025 252 c40 - 4200 505 203 s92 - 1587 1025 253 c4 1 - 4200 445 204 s93 - 1647 1025 254 c42 - 4200 385 205 s94 - 1707 1025 255 c43 - 4200 325 206 s95 - 1767 1025 256 c44 - 4200 265 207 s96 - 1827 1025 257 c45 - 4200 205 208 s97 - 1887 1025 258 c46 - 4200 145 209 s98 - 1947 1025 259 c47 - 4200 85 210 s99 - 2 007 1025 260 c48 - 4200 25 211 s100 - 2067 1025 261 c49 - 4200 - 35 212 s101 - 2127 1025 262 c50 - 4200 - 95 213 s102 - 2187 1025 263 c51 - 4200 - 155 214 s103 - 2247 1025 264 c52 - 4200 - 215 215 s104 - 2307 1025 265 c53 - 4200 - 275 216 s105 - 2367 1025 266 c54 - 4200 - 335 217 s106 - 2427 1025 267 c55 - 4200 - 395 218 s107 - 2487 1025 268 c56 - 4200 - 455 219 s108 - 2547 1025 269 c57 - 4200 - 515 220 s109 - 2607 1025 270 c58 - 4200 - 575 221 s110 - 2667 1025 271 c59 - 4200 - 635 222 s111 - 2727 1025 272 c60 - 4200 - 695 223 s112 - 2787 1025 273 c61 - 4200 - 755 224 s113 - 2847 1025 274 c62 - 4200 - 815 225 s114 - 2907 1025 275 c63 - 4200 - 875 226 s115 - 2967 1025 276 comm - 4200 - 935 227 s116 - 3027 1025 228 s117 - 3087 1025 229 s118 - 3147 1025 230 s11 9 - 3207 1025 231 s120 - 3267 1025 232 s121 - 3327 1025 233 s122 - 3387 1025 234 s123 - 3447 1025 235 s124 - 3507 1025 236 s125 - 3567 1025 237 s126 - 3627 1025 238 s127 - 3687 1025 239 s128 - 3747 1025 240 s129 - 3807 1025 241 s130 - 3867 1025 242 s131 - 3927 1025 243 dummy4 - 4119 1025 244 c32 - 4200 985 245 c33 - 4200 925 246 c34 - 4200 865 247 c35 - 4200 805 248 c36 - 4200 745 249 c37 - 4200 685 250 c38 - 4200 625 nju6676 preliminary block diagram c0 - - - - c31 c63 - - - - c32 s0 - - - - - - - - - - - - - s131 comm vss vdd v1 to v5 c1+/c1- c2+/c2- c3- vout vss2 vr cs2 a0 c86 d7 (si) d6 (scl) d5 to d0 res cs1 wr rd reset mpu interface instruction decoder status busy flag bus holder internal bus line multiplexer colum address register colum address counter colum address recoder page address register ocsailator display timing line counter line address decoder low address decoder common direction display data ram 65 x 132 = 8,580-bit display data latch segment drivers common drivers common drivers shift register shift register voltage converter common timing osc1 osc2 voltage regulator voltage followers internal power circuits m/s fr cl dof frs cls initial display line add p/s nju6676 preliminary terminal description power supply peripheral no. symbol description 11,17 26 29 51,52 65 67 73,75 vdd vdd=+3v 8,14, 3031, 32,49 50,70,74 vss vss=0v 33 36 vss2 reference voltage for voltage booster lcd driving voltage supplying terminal. when the internal voltage booster is not used, supply each level of lcd driving voltage from outside with following relation. vdd v1 v2 v3 v4 v5 when the internal power supply is on, the internal circuits generate and supply following lcd bias voltage from v1 to v4 terminal. bias v1 v2 v3 v4 1/7 bias v5+6/7vlcd v5+5/7vlcd v5+2/7vlcd v5+1/7vlcd 1/9 bias v5+8/9vlcd v5+7/9vlcd v5+2/9vlcd v5+1/9vlcd 53,54 55,56 57,58 59,60 61,62 v1 v2 v3 v4 v5 (vlcd=vdd-v5) lcd driving power supply peripheral no. symbol description 41,42 43,44 c1+ c1- boosted capacitor connecting terminals used for voltage booster. 47,48 45,46 c2+ c2- boosted capacitor connecting terminals used for voltage booster. 39,40 c3- boosted capacitor connecting terminals used for voltage booster. 37,38 vout voltage booster output terminal. connect the boosted capacitor between this terminal and vss2. 63,64 vr voltage adjust terminal. v5 level is adjusted by external bleeder resistance connecting between vdd and v5 terminal. interface peripheral no. symbol description 18 25 (24,25) d0 d7 (scl, si) p/s="h" : tri-state bi-directional data i/o terminal in 8-bit parallel operation. p/s="l" : d7=serial data input terminal. d6=serial data clock signal inpu t terminal. data from si is loaded at the rising edge of scl and latched as the parallel data at 8th rising edge of scl. connect to the address bus of mpu. the data on the d0 to d7 is distinguished between display data and instruction by status of a0. a0 h l distin . display data instruction 13 a0 12 res reset terminal. when the res terminal goes to ?l?, the initialization is performed. reset operation is executing during ?l? state of res. 9 10 cs1 cs2 chip select terminal. data input/output are available during cs1=?l? and cs2=?h?. nju6676 preliminary no. symbol description 16 rd (e) nju6676 preliminary no. symbol description display clock input/output terminal. the following is true depending on the m/s and cls status. m/s cls cl ?h? output ?h? ?l? input ?l? * input 6 cl *:don?t care 5 fr lcd alternating current signal i/o terminal. m/s = ?h? : output m/s = ?l? : input lcd display blanking control terminal. m/s = ?h? : display ?on? = ?h?, display ?off? = ?l? m/s = ?l? : external control. refer to the following table. dof command h l display on? on off display off? off off 7 dof 4 frs the output terminal for the static drive. this terminal is used in conjunction with the fr terminal. lcd drivers no. symbol description 77 108 c31 c0 lcd driving signal output terminals. -segment output terminals : s0 s131 -common output terminal : c0 c63 segment output terminal the following output voltages are selected by the combination of fr and data in the ram. output voltage ram data fr normal reverse h vdd v2 h l v5 v3 h v2 vdd l l v3 v5 111 242 s0 s 131 common output terminal the following output voltages are selected by the combination of fr and status of common. scan data fr output voltage h v5 h l vdd h v1 l l v4 244 275 c 32 c 63 109, 276 comm com output terminals for the indicator. both terminals output the same signal. leave these open if they are not used. (terminals 1,76,110,243 are dummy pad) nju6676 preliminary functional description (1) block circuits description (1 - 1) busy flag (bf) during internal operation, the lsi is being busy and can ? t accept any instructions except ? status read ? . the bf data is output through d7 terminal by the ? status read ? instruction. when the cycle time (tcyc) mentioned in the ? ac characteristics ? is satisfied , the bf check isn ? t required after each instruction, so that mpu processing performance can be improved. (1 - 2) initial display line register the initial display line register assigns a ddram line address, which corresponds, to com0 by ? initial display line set ? instruction . it is used for not only normal display but also vertical display scr olling and page switching without changing the contents of the ddram. however, the 65 th address for icon display can ? t be assigned for initial display line address. (1 - 3) line counter the line counter provides a ddram line address . it initializes its cont ents at the switching of frame timing signal (fr), and also counts - up in synchroniz ation with common timing signal. (1 - 4) column address counter the column address counter is an 8 - bit preset counter which provides a ddram column address, and it is indepen dent of below - mentioned page address register . it will increment (+1) the column address whenever ? display data read ? or ? display data write ? instructions are issued. however, the counter will be locked when no - existing address above (84)h are addressed. t he count - lock will be able to be released by the ? column address set ? instruction again. the counter can invert the correspondence between the column address and segment driver direction by means of ? adc set ? instruction. (1 - 5) page address register the p age address register provides a ddram page address. the last page address ? 8 ? should be used for icon display because the only d0 is valid. (1 - 6) display data ram (ddram) the ddram contains 8,580 - bit, and stores display data which is 1 - to - 1 correspondents to lcd panel pixels. when normal display mode, the display data ? 1 ? turns on and ? 0 ? turns off lcd pixels . when inverse display mode, ? 1 ? turns off and ? 0 ? turns on. nju6676 preliminary fig.1 display data ram (ddram) map page address data display pattern line addres s common driver d0 (00)h com0 d1 01 com1 d3,d2,d1,d0 d2 02 com2 (0,0,0,0) d3 page 0 03 com3 d4 04 com4 d5 05 com5 d6 06 com6 d7 07 com7 d0 n n 08 com8 d1 n n 09 com9 d3,d2,d1,d0 d2 n n n 0a com10 (0,0,0,1) d3 n n n page 1 0b com11 d4 n n n 0c com12 d5 n n 0d com13 d6 n n 0e com14 d7 0f com15 d0 10 com16 d1 11 com17 d3,d2,d1,d0 d2 12 com18 (0,0,1,0) d3 page 2 13 com19 d4 14 com20 d5 15 com21 d6 16 com22 d7 17 com23 d0 18 com24 d1 19 com25 d2 1a com26 : : : : : : : : : : : : : : : : : : : : d5 35 com53 d6 36 com54 d7 37 com55 d0 38 com56 d1 39 com57 d3,d2,d1,d0 d2 3a co m58 (0,1,1,1) d3 page 7 3b com59 d4 3c com60 d5 3d com61 d6 3e com62 d7 3f com63 (1,0,0,0) d0 page 8 * comi column adc ? 0 ? 00 01 02 03 04 05 06 82 83 address ? 1 ? 83 82 81 80 7f 7e 7d 01 00 segment drivers 0 1 2 3 4 5 6 130 131 initial note ) comi is independent of the ? initial display line se t ? instruction and always corresponds to the 65 th line. for example the initial display is 08h. nju6676 preliminary (1 - 7) common direction register the common direction register specifies common driver ? s scanning direction. common drivers register a3 pad no. 108 77 275 244 pin name c0 ------------------------------ c31 c63 ---------------------------- c32 0 com0 ------------------ com31 com63 ----------------- com32 1 com63 ----------------- com32 com0 ---- -------------- com31 (1 - 8) reset circuit the reset circuit initializes the lsi to the following status by using of the reset signal into the res terminal. reset status using the res terminal: 1. lcd driver set off 2. display off 3. normal display (non - inver se display) 4. adc select : normal mode (d0=0) 5. power control register clear 6. serial interface register clear 7. lcd bias select : 1/9 bias 8. read modify write off 9. static indicator off 10. initial display line address : (00)h 11. column address : (00)h 12. page address : (0) p age 13. common direction register : normal mode (d3=0) 14. evr mode off and evr register : (20)h 15. test mode off 16. entire display off : normal mode the res terminal should be connected to mpu ? s reset terminal, and the reset operation should be executed at the same timing of the mpu reset. as described in the ? dc characteristics ? , it is necessary to input 10us or over ? l ? level signal into the res terminal in order to carry out the reset operation. the lsi will return to normal operation after about 1us from the r ising edge of the rest signal. in case of using external power supply for lcd driving voltage, the res terminal is required to be being ? l ? level when the external power supply is turned - on. the ? reset ? instruction in table.4 can ? t be substituted for the reset operation by using of the res terminal. it executes above - mentioned only 8 to 16 items. (1 - 9) lcd display circuits a) common and segment drivers lcd drivers consist of 64 - common drivers, 132 - segment divers and 1 - icon - common driver. as shown in fig.7, lcd driving waveforms are generated by the combination of display data, common timing signal and internal fr timing signal. nju6676 preliminary b) display data latch circuit the display data latch circuit temporally stores 132 - bit display data transferred from the ddram i n the synchroniz ation with the common timing signal, and then it transfers these stored data to the segment drivers. ? display on/off ? , ? inverse display on/off ? and ? entire display on/off ? instructions control only the contents of this latch circuit, they c an ? t change the contents of the ddram. in addition, the lcd display isn ? t affected by the ddram accuses during its displaying because the data read - out timing from this latch circuit to the segment drivers is independent of accessing timing to the ddram. c) line counter and latch signal or latch circuits the clock line counter and latch signal to the latch circuits are generated from the internal display clock (cl). the line address of display data ram is renewed synchronizing with display clock (cl). 132 bits display data are latched in display latch circuits synchronizing with display clock, and then output to the lcd driving circuits. the display data transfer to the lcd driving circuits is executed independently with ram access by the mpu. d ) display timing generator the display timing generates the timing signal for the display system bay combination of the master clock cl and driving signal fr ( refer to fig.2 ) the frame signal fr and lcd alternative signal generate lcd driving waveform on the two frame alternative driving method. e) common timing generation the common timing is generated by display clock cl (refer to fig.2) fig.2 display timing 64 63 1 2 3 4 5 6 7 8 64 63 1 2 3 4 5 6 7 8 cl fr com0 com1 ram data seg n fig.2 waveform of display timing nju6676 preliminary f) oscillator this is the low power consumption cr oscillator which provides the display clock and voltage converter - timing clock . e) internal power circuits the internal power circuits are composed of x4 boost voltage converter, output voltage regulator including 64 - step evr and voltage followers. the optimum values of the external passive components for the internal power circuits, such as capacitors for v1 to v5 terminals and feed back resistors for vr terminal , depend on lcd panel size. therefore, it is necessary to evaluate the actual lcd module with these external c omponents in order to determine the optimum values. each portion of the internal power circuits is controlled by ? power control set ? instruction as shown in table.1. in addition , the combination of power supply circuits is described in table.2. table. 1) power control set bits portions status d2 voltage converter 1 :on 0: off d1 voltage regulator 1 :on 0: off d0 voltage followers 1 :on 0: off table. 2) power supply combinations status d2 d1 d0 voltage converter voltage regulator voltage followers ex ternal voltage capacito r terminals using all internal power circuits 1 1 1 on on on vss2 use using voltage regulator and voltage followers 0 1 1 off on on vout, vss2 open using voltage followers 0 0 1 off off on v5, vss2 open using only external power supply 0 0 0 off off off v1 to v5 open note1) capacitor input terminals: c1+, c1 - , c2+, c2 - , c3 - note2) do not use other combinations except examples in table.2. note3) connect decoupling capacitors on v1 to v5 terminals w henever using the voltage follow ers. nju6676 preliminary (2) instruction set the d7 to d0 data is distinguished as display data or instruction data by the combination of a0, rd and wr signals. table.3 instruction table instruction code instruction ao rd wr d7 d6 d5 d4 d3 d2 d1 d0 description 1 display on/ off 0 1 0 1 0 1 0 1 1 1 0 1 0 :off 1 :on 2 initial display line set 0 1 0 0 1 d5 d4 d3 d2 d1 d0 specify ddram line address for com0 3 page address set 0 1 0 1 0 1 1 d3 d2 d1 d0 ddram page address 4 column address set upper 4 - bit column address set lowe r 4 - bit 0 0 1 1 0 0 0 0 0 0 0 0 1 0 d3 d3 d2 d2 d1 d1 d0 d0 ddram column address of upper 4 - bits ddram column address of lower 4 - bits 5 status read 0 0 1 d7 d6 d5 d4 0 0 0 0 read internal status 6 display data write 1 1 0 d7 d6 d 5 d4 d3 d2 d1 d0 write ddarm data 7 display data read 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 read ddram data 8 adc select 0 1 0 1 0 1 0 0 0 0 0 1 select segment direction 9 inverse display on/off 0 1 0 1 0 1 0 0 1 1 0 1 0 : normal display 1 : inverse display on 10 entire display on/off 0 1 0 1 0 1 0 0 1 0 0 1 0 : normal display 1 : entire display on 11 lcd bias select 0 1 0 1 0 1 0 0 0 1 0 1 0 : 1/9 bias 1 : 1/7 bias 12 read modify write 0 1 0 1 1 1 0 0 0 0 0 increment column address 13 end 0 1 0 1 1 1 0 1 1 1 0 release read modify write 14 reset 0 1 0 1 1 1 0 0 0 1 0 internal reset 15 common direction select 0 1 0 1 1 0 0 0 1 * * * select common direction 16 power control set 0 1 0 0 0 1 0 1 d2 d1 d0 set the status of internal power circuits 17 driver on/ off 0 1 0 1 1 1 0 0 1 1 0 1 0 : driver off 1 : driver on 18 evr mode set evr register set 0 0 1 1 0 0 1 * 0 * * 0 d5 0 d4 0 d3 0 d2 0 d1 1 d0 set evr mode set evr register 19 static indicator on/off static indicator register set 0 0 1 1 0 0 1 * 0 * 1 * 0 * 1 * 1 * 0 d1 0 1 d0 0 : off 1 : on set static indicator register 20 power save mode on/off - - - - - - - - - - - dual commands of display off & entire display on 21 nop 0 1 0 1 1 1 0 0 0 1 1 22 test 0 1 0 1 1 1 1 * * * * don ? t use nju6676 preliminary (3) instruction description 3 - 1) display on/off this instruction selects display turn - on or turn - off regardless of the contents of the ddram. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 display on or off 0 1 0 1 0 1 0 1 1 1 0 1 0 :off 1 :on 3 - 2) initial display line set this instruction specifies the ddram line address which corresponds to the com0 position. by means of repeating this instruction , the initial display line address will be dynamically changed; it means smo oth display scrolling will be enabled. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 line address for com0 0 1 0 0 1 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 0 1 : 62 63 3 - 3) page address set in order to access to the ddram for writing or readin g display data, both ? page address set ? and ? column address set ? instructions are required before accessing. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 page address 0 1 0 1 0 1 1 0 0 : 0 1 0 0 : 1 0 0 0 : 1 0 0 1 : 1 0 0 1 : 7 8 nju6676 preliminary 3 - 4) column a ddress set as above - mentioned , in order to access to the ddram for writing or reading display data, it is necessary to execute both ? page address set ? and ? column address set ? before accessing. the 8 - bit column address data will be valid when both upper 4 - bit and lower 4 - bit data are set into the column address register. once the column address is set, it will automatically increment (+1) whenever the ddram will be accessed, so that the ddram will be able to be continuously accessed without ? column address set ? instruction. the column address will stop increment and the page address will not be changed when the last address (83 )h is addressed. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 0 0 1 0 a7 a3 a6 a2 a5 a1 a4 a0 upper 4 - bit lower 4 - bit a7 a6 a 5 a4 a3 a2 a1 a0 column address 0 0 : 1 1 0 0 : 0 0 0 0 : 0 0 0 0 : 0 0 0 0 : 0 0 0 0 : 0 0 0 0 : 1 1 0 1 : 0 1 0 1 : 130 131 3 - 5) status read this instruction reads out the internal status regarding ? busy flag ? , ? adc select ? , ? display on/off ? an d ? reset ? . a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 busy adc on/off reset 0 0 0 0 busy : when d7 is ? 1 ? , the lsi is being busy and can ? t accept any instructions. adc : it shows the correspondence between the column address and segment drivers. whe n d6 is ? 0 ? , the column address (131 - n) corresponds to segment driver n. when d6 is ? 1 ? , the column address (n) corresponds to segment driver n. please be careful that read out data is opposite of ? adc select ? instruction data. on/off : it shows dis play on or off status. when d5 is ? 0 ? , the lsi is in display - on status. when d5 is ? 1 ? , the lsi is in display - off status. please be careful that read out data is opposite of ? adc select ? instruction data. reset : it shows reset status. when d4 is ? 0 ? , the lsi is in normal operation. when d4 is ? 1 ? , the lsi is during reset operation. nju6676 preliminary 3 - 6) display data write this instruction writes display data into the selected column address on the ddram. the column address automatically increments (+1) whenever the display data is written by this instruction, so that this instruction can be continuously issued without ? column address set ? instruction. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 write data 3 - 7) display data read this instruction reads out the display data stored in the selected column address on the ddram. the column address automatically increments (+1) whenever the display data is read out by this instruction, so that this instruction can be continuously issued without ? column address set ? instruction. after the ? column address set ? instruction, a dummy read will be required, please refer to the (5 - 4). in case of using serial interface mode, this instruction can ? t be used. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 read data 3 - 8) adc select this instruction selects segment driver direction. the correspondence between the column address and segment driver direction is shown in fig.1. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 segment driver direction 0 1 0 1 0 1 0 0 0 0 0 1 normal invers e 3 - 9) inverse display on/off this instruction inverses the status of turn - on or turn - off of entire lcd pixels . it doesn ? t change the contents of the ddram. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 display status 0 1 0 1 0 1 0 0 1 1 0 1 normal inverse 3 - 10 ) entire display on/off this instruction turns on entire lcd pixels regardless the contents of the ddram. it doesn ? t change the contents of ddram. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 entire display on/off 0 1 0 1 0 1 0 0 1 0 0 1 normal entire display on nju6676 preliminary 3 - 11) lcd bias set this instruction selects lcd bias value. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 lcd bias 0 1 0 1 0 1 0 0 0 1 0 1 1/9 1/7 3 - 12) read modify write this instruction controls column address increment. by using of this instruction, the col umn address can ? t increment when read operation but it can increment when write operation. this status will be continued until the below - mentioned ? end ? instruction will be issued. this instruction can reduce the load of mpu, during the display data in sp ecific ddram area is repeatedly changed for cursor blink or others. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 1 1 0 0 0 0 0 the sequence of cursor blink display page address set column address set read modi fy write data read data write dummy read data read data write dummy read end finish ? set address for cursor line start ? read modify inverse data in mpu end ? read modify repeat no yes nju6676 preliminary 3 - 13) end the ? end ? instruction cancels the read modify write mode and makes the column address return to the initial value just before ? read modify write ? is started. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 1 1 0 1 1 1 0 3 - 14) reset this instruction reset the lsi to the following status , however it doesn ? t change the contents of the ddram. please be careful that it can ? t be substituted for the reset operation by using of the res terminal. reset status by ? reset ? instruction: 1. read modify write off 2. static indicator off 3. initial display line address : (00)h 4. column address : (00)h 5. page address : (0) page 6. common direction register : normal mode (d3=0) 7. evr mode off and evr register : (20)h 8. test mode off a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 1 1 0 0 0 1 0 3 - 15) common driver direction select this instruction selects common driver direction. please refer to (1 - 7) common driver direction for more detail. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 common driver direction 0 1 0 1 1 0 0 0 1 * * * normal inve rse column addre ss n n+m n+3 n+2 n+1 n return read modify write end nju6676 preliminary 3 - 16) power control set this instruction controls the status of internal power circuits. please refer to the (4) internal power supply circuits for more detail. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 status 0 0 1 0 1 0 1 voltage converte r off voltage converter on 0 1 voltage regulator off voltage regulator on 0 1 0 0 1 voltage followers off voltage followers on note) the internal power supply must be off when external power supply using. * the wait time depends on t he c3 to c7, cout capacitors , and vdd and vlcd voltage. therefore it requires the actual evaluation using the lcd module to get the correct time. 3 - 17) lcd driver on/off this instruction controls lcd driving waveform output through the com/seg terminals. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 driver 0 1 0 1 1 1 0 0 1 1 0 1 off on the nju6676 contains low power lcd driving voltage generator circuit reducing own operating current . therefore , it requires the following sequence procedures at power on for power source stabilized operation. t.b.d nju6676 preliminary lcd driving power supply on/off sequences the following sequences required when the power supply is turned on/off. when the power supply is turned on again after the turn off (by the power save instruction), the power save release sequence(3-22) is required. turn on sequence turn off sequence 3-18) evr mode set this instruction sets the lsi into the evr mode, and it is always used by the combination with ?evr register set?. the lsi can?t accept any instructions except the ?evr register set? during the evr set mode. this mode will be released after the ?evr register set? instruction. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 0 0 0 0 0 1 3-19) evr register set this instruction sets 6-bit data into the evr register to determine the output voltage ?v5? of the internal voltage regulator. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 v5 0 1 0 * * 0 0 : 1 1 0 0 : 1 1 0 0 ; 1 1 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 minimum maximum 3-20) static indicator on/off this instruction selects static indicator turn-on or turn-off, and it is always used by the combination with the ? static indicator register set?. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 static indicator 0 1 0 1 0 1 0 1 1 0 0 1 off on output assign. register set static indicater set lcd driver on internal power supply on or external power suppl y on evr register set wait time display off entire display off lcd drivier off internal power supply off or external power su pp l y off nju6676 preliminary 3 - 21) static indicator register set this instruction sets 2 - bit data into the static indicator register. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 status 0 1 0 * * * * * * 0 0 1 1 0 1 0 1 off on (blink at 1.0 s intervals) on (blink at 0.5s intervals) on (turn on at all time) 3 - 22) power save mode on/off this instruction sets the lsi into the power save mode by the combination of ? display off ? and ? whole displa y on ? instructions for reducing operating current as well as static operation ? s. the internal status and the contents of the ddram will be remained just before the ? power save mode on/off ? instruction. in addition, the ddram can be accessed during the powe r save mode. there are two power save modes, sleep mode and standby mode. during sleep mode: all lcd system stops as follows, 1. oscillator and internal power circuits stop. 2. all common and segment drivers output vdd level. during standby mode: the lc d system except the static indicator stops as follows, 1. oscillator and internal power circuits stop. 2. all common and segment drivers output vdd level. 3. the only static indicator is op erating. fig.5 the sequence of power save mode static indicator off static indicator on power save on (dual instructions) sleep mode standby mode power save off power save off entire display off + static indicator on entire display off release sleep mode release standby mode nju6676 preliminary (4) internal power circuits (a)voltage converter the voltage converter generates maximum 4x boosted negative - voltage from the voltage between vdd and vss2. the boosted voltage is output from the vout terminal. the internal oscillator is required to be oper ating when using this converter, because the divided signal provided from the oscillator is used for the internal timing of this circuit. the boosted voltage between vdd and vout must not exceed 18.0v. the voltage converter requires external capacitors for boosting as shown in fig.7. fig.7 the capacitors connection for the voltage regulator: 4x boost 3x boost 2x boost vss2 vout c3 - c1+ c1 - c2 - c2+ + + + vss2 vout c3 - c1+ c1 - c2 - c2+ + + + vss2 vout c3 - c1+ c1 - c2 - c2+ + + vdd vss2 vout= 4x (vdd - vss2) vdd vss2 vout= 3x (vdd - vss2) vdd vss2 vout= 2x (vdd - vss2) nju6676 preliminary (b)contrast control using the voltage regulator the voltage regulator determines the lcd driving voltage ?v5? according to the rb/ra ratio and vreg voltage. the equations to calculate v5 are as follows: fig.5 voltage regulator circuit (c)contrast control voltage vreg as the equation [2] shows, the vreg value depends on the parameter ?n?. the ?n? is selected a value within 99 to 162 by using of ?evr register set? instruction as described in table.8. table.8 the relationship between evr register and vlcd level register value d5 d4 d3 d2 d1 d0 n vreg 00 0 0 0 0 0 0 99 (99/162) x (vdd-vss2) minimum 01 0 0 0 0 0 1 100 (100/162) x (vdd-vss2) : 02 0 0 0 0 1 0 101 (101/162) x (vdd-vss2) : : : : : : : : : : 61 1 1 1 1 0 1 160 (160/162) x (vdd-vss2) : 62 1 1 1 1 1 0 161 (161/162) x (vdd-vss2) : 63 1 1 1 1 1 1 162 (162/162) x (vdd-vss2) maximum vlcd : lcd driving voltage ra, rb : feed back resistors vreg : contrast control voltage n : parameter decided instruction rb ra vreg vr v5 vdd + - vlcd volta g e re g ulator vout vlcd = vdd ? v5 = (1+rb/ra) x vreg ---[1] vreg = (n/162) x (vdd-vss2) ---[2] nju6676 preliminary - vlcd setting example we recommend the total value of ra and rb is between 1m w and 5m w . when using ra=1m w , rb=4m w and vdd=3v, the vlcd is calculated as follows: the minimum vlcd: vlcd =(1+rb/ra) x vreg =(1+4/1) x [(99/162) x 3.0] =9.15v the maximum vlc d: vlcd =(1+rb/ra) x vreg =(1+4/1) x [(162/162) x 3.0] =15.0v nju6676 preliminary (d) lcd driving voltage generation circuits the lcd driving bias voltage of v1,v2,v3,v4 are generated internally by dividing the v5 voltage with the internal bleeder resistance. and it is supplied to the lcd driving circuits after the impedance conversion with voltage follower circuit. as shown in below, five capacitors are required to connect to each lcd driving voltage terminal for voltage stabilizing. and the value of capacitors c4, c5, c6, c7, and c8 are determined depending on the actual lcd panel display evaluation. using the internal power supply using the external power supply *1 short wiring or sealed wiring to the vr terminal is required due to the high impedance of vr terminal. *2 following connection of vout is required when external power supply using. when vss > v5 --- vout=v5 when vss < v5 --- vout=vss vss c1- c1+ c3- c2+ vr vout c2- nju6676 v5 vdd v1 v2 v3 v4 v5 external voltage generator + + vss vss2 c1- c1+ c3- c2+ vr vout c2- nju6676 v5 vdd v1 v2 v3 v4 v5 + + + + + c4 c5 c6 c7 c8 c1 c3 c2 cout r2 r1 r3 1 ! 2 + reference set up value vlcd=vdd-v5=9.0 to 10.5v cout c1/c2/c3 c4 c8 r1 r2 r3 1.0 f 1.0 f 0.1 0.47 f 2m 500k 2.5m nju6676 preliminary (5) mpu interface (5 - 1) interface type selection nju6676 interfaces with mpu by 8 - bit bidirectional data bus (d7 to d0) or serial (si:d7). the 8 bit parallel or serial interface is determined by a condition of the p/s terminal connecting to "h" or "l" level as shown in table 4. in case of the serial interface, status and ram data read out operation is impossible. table4 p/s type cs1 a0 rd wr c86 si(d7) scl(d6 ) d0 ~ d5 h parallel cs1 a0 rd wr c86 d7 d6 d0 ~ d5 l serial cs1 a0 - - - si scl hi - z ? - ? : they should be fixed to ? h ? or ? l ? . (5 - 2) parallel interface the nju6676 interfaces to 68 or 80 type mpu directly when the parallel interface (p/s="h") is selected. 68 type mpu or 80 is determined by the condition o f c86 terminal connecting to "h" or "l" as shown in table 5. table 5 c86 type cs1 a0 rd wr d0 ~ d7 h 68 type mpu cs1 a0 e r/w d0 ~ d7 l 80 type mpu cs1 a0 rd wr d0 ~ d7 (5 - 3) discrimination of data bus signal the nju6676 discriminates the mean of signal on the data bus by the combination of a0, e, r/w, and (rd,wr) signals as shown in table 6. table 6 common 68 type 80 type a0 r/w rd wr function 1 1 0 1 read display data 1 0 1 0 write display data 0 1 0 1 status read 0 0 1 0 write into the register(in struction) nju6676 preliminary (5 - 4) serial interface.(p/s="l") serial interface circuits consist of 8 bits shift register and 3 bits counter. si and scl input are activated when the chip select terminal cs1 set to "l"and p/s terminal set to "l". the 8 bits shift regis ter and 3 bits counter are reset to the initial condition when the chip is not selected. the data input from si terminal is msb first like as the order of d7,d6, - - - - d0, and the data are entered into the shift register synchronizing with the rise edge of the serial clock scl. the data in the shift register are converted to parallel data at the 8th serial clock rise edge input. discrimination of the display data or instruction of the serial input data is executed by the condition of a0 at the 8th seri al clock rise edge. a0="h" is display data and a0="l" is instruction. when res terminal becomes "l" or cs1 terminal becomes "h" before 8th serial clock rise edge, nju6676 recognizes them as a instruction data incorrectly. therefore a unit of serial data must be structured by 8 - bit. the time chart for the serial interface is shown in fig. 5. to avoid the noise trouble, the short wiring is required for the scl input. note) the read out function, such as the status or ram data read out, is not supported in this serial interface fig.5 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 cs1 si cs2 scl a0 1 2 3 4 5 6 7 8 9 10 nju6676 preliminary 5 - 5) access to the display data ram and internal register. the nju6676 is operating as one of pipeline processor by the bus - holder connecting to the internal data bus to adjust the operation frequency between mpu and the display data ram or internal register. for example, when the mpu reads out the data from the display data ram, the read out data in the data read cycle (dumm y read) is held in the bus - holder, then it is read out from the bus - holder to the system bus at the next data read cycle. when the mpu writes the data into the display data ram, the data is held in the bus - holder, then it is written into the display data ram by the next data write cycle. therefore high speed data transmission between mpu and nju6676 is available because of it is not limited by the tacc and tds as display data ram access time and is limited by the system cycle time (r) or (w). if the cycle time is not be kept in the mpu operation, nop should be inserted to the system instead of the waiting operation. the read out operation does not read out the data in the pointed address just after the address set operation. and second read out operation can read out the data correctly from the pointed address. therefore, one dummy read operation is required after address setting or write cycle as shown in fig. 6.. fig.6 n n+1 n+2 n+3 n n+1 n+2 n+3 wr data bus holder wr mpu signal internal signal write timing read timing n n n n +1 wr data rd address set dummy read data read data read mpu signal n n+1 n+2 n n n +1 wr rd bus holder column address internal signal nju6676 preliminary 5 - 5) chip select cs1, cs2 are chip select terminals. in case of cs1="l" and cs2= ? h ? , the interface with mpu is available. in case of cs1= ? h ? or cs2= ? l ? , the d0 to d7 are high impedance and a0, rd, wr, d7(si) and d6(scl) inputs are ignored. if the serial interface is selected when cs1= ? h ? or cs2= ? l ? , the shift register and the counter are reset. however, the reset is always operated in any conditions of cs1 and cs2. nju6676 preliminar y n absolute maximumn ratings ta=2 5 c parameter symbol ratings unit supply voltage vdd - 0.3 to +7.0 v supply voltage vss2 - 7.0 to+0.3 - 6.0 to +0.3 (when using 3x voltage converter) - 4.5 to +0.3 (when using 4x voltage converter) v supply voltage v5 vout - 18.0 to +0.3 v supply voltage v1,v2 v3,v4 v5 to +0.3 v input voltage vin - 0.3 to vdd+0.3 v operating temperature topr - 30 to +80 c storage temperature tstg - 55 to +100 (tcp) c - 55 to +125 (chip) note1) all voltages are relative to the v s s = 0v reference. the relationship among the supply voltages should be maintained the following condition. vd d > v 0 > v 1 > v 2 > v3 > v4 > v5;vdd>vs s > vout note2) when using the external power supply for lcd driving , the external power should be turn on at the same timing of v dd or after vdd. note3) the lsi should be operated inside of the absolute maximum ratings in order to prevent excessive stress. otherwise, the stresses beyond the absolute maximum ratings may cause permanent damage to the lsi. note4) the decoupling capa c itor between vdd terminal and vss terminal is required in order to stabilize the lsi operation. nju6676 preliminary dc electrical characteristics vdd=2.7v to 3.3v, vss=0v, ta=-30 to +80 c parameter symbol conditions min. typ. max. unit note power supply(1) vdd recommend 2.7 - 3.3 v 5 possible 2.2 - 5.5 v power supply(2) vss1 vdd-6.0 - vdd-2.5 v power supply(3) v5 vlcd=vdd-v5 vdd-18 - vdd-6 v v1,v2 0.4xv5 - vdd v v3,v4 v5 - 0.6xv5 v ?h? level input voltage vihc1 0.8vdd - vdd v ?l? level input voltage vilc1 vss - 0.2vdd v ?h? level output voltage vohc1 ioh=-0.5ma 0.8vdd - vdd v ?l? level output voltage volc1 io=0.5ma vss - 0.2vdd v input leakage current ili -1.0 - 1.0 ua output leakage current ilo -3.0 - 3.0 ua ron1 vlcd=14.0v, ta=25 c - 2.0 3.5 k ? lcd on resistance ron2 vlcd=8.0v, ta=25 c - 3.2 5.4 k ? 6 input pin capacitance cin ta=25 c - 10 - pf 9 oscillation frequency fosc ta=25 c 18 22 26 khz reset time tr using res terminal 1.0 - - us 10 reset pulse width trw 10 - - us 11 internal power supply parameter symbol conditions min. typ. max. unit note input voltage vdd1 vdd-vss using 3x voltage converter -6.0 - -2.5 v vdd2 vdd-vss using x4 voltage converter -4.5 - -2.5 v 12 voltage converter output voltage vout -18.0 - - v voltage converter output on resustance rstep c1 to c3, cout=1.0uf using x4 booster - 2500 3500 ? volateg regulator operating voltage vout voltage converter off vdd -18.0v - vdd -6.0v v 13 voltage follower operating voltagae v5 voltage regulator off vdd -18.0v - vdd -6.0v v operating current iddq1 when sleep mode - 0.01 5.0 ua 14 iddq2 when standby mode - 4 10 ua idd1 vdd=3v, v5=-11v - 80 140 ua idd2 checker flag display - 20 40 ua idd3 without mpu access - 18 35 ua idd4 all com/seg open - 15 30 ua reference voltage v reg vdd=3v, ta=25 c 3.0 % note5) this parameter can?t be guaranteed for spike voltage during mpu access. note6) apply to the resistance between each driver (com, seg) and power supply terminal (v1,v2,v3,v4) when 0.1v voltage difference is supplied between these terminals. note7,8)apply to the condition when internal power circuits aren?t used. note7) apply to the condition when mpu doesn?t access to the lsi. note8) apply to the condition when writing checker flag pattern to the ddram at the timing of tcyc. note9) apply to a0, d7 to d0, rd, wr, cs, res, c86 and p/s terminals. note10) specified the time between the rising edge of the res signal and completion of reset operation. nju6676 preliminar y note11) specified t h e minimum pulse width of res signal. note12) apply to thevdd when using quadrupler. note13) lcd driving voltage can be adjusted within the voltage follower operating range. note14) e ach value are specified in the following conditions: power control operating condition symbol d2 d1 d0 voltage converter voltage regulator voltage followers external voltage supply (input terminal) iout1 1 1 1 on on on use(vss2) iout2 0 1 1 off on on use(vout,vss2) iout3 0 0 1 off off on use(v5,vss2) iout4 0 0 0 off off off use(v 1 ~ v5) idd 1,2,3,4 measurement circuits: idd1 idd2 idd3 2+ c 1 - c1+ c3 - c2 - + + + vss vout v5 vr vdd a vss v5 vr vdd a c2+ c 1 - c1+ c 3 - c2 - vout vss v5 vr vdd a c2+ c 1 - c1+ c 3 - c2 - vout nju6676 preliminar y idd4 vss v5 vr vdd a c2+ c1 - c1+ c3 - c2 - vout v4 v3 v2 v1 v1 v2 v3 v4 nju6676 preliminar y n bus timing characteristics read and write characteristics (80 type mpu) (vss=0v, vdd=4.5 to 5.5v, ta= - 30 to 80 c) parameter terminal symbol condition min. max. unit address hold time tah8 0 - ns address set up time a0,cs1, cs2 taw8 0 - ns system cycle time tcyc8 166 - ns control ? h ? pulse width (read) tcchr 30 - ns control ? h ? pulse width ( write ) tcchw 70 - ns control ? l ? pulse width (read) tcclr 30 - ns control ? l ? pulse width ( write ) wr,rd tcclw 30 - ns data set up time tds8 30 - ns data hold time tdh8 10 - ns rd access time tacc8 - 70 ns output disable time d7 ~ d0 toh8 cl=100pf 5 50 ns input signal rising, falling edge cs1,cs2 rw,rd,a0, d7 ~ d0 tr,tf 15 ns a0,cs1,cs2 wr,rd tcyc8 taw8 tah8 tcch tccl tds8 tdh8 d7 to d0 write tf tr toh8 tacc8 d7 to d0 read nju6676 preliminar y (vss=0v, vdd=2.7 to 4.5v, ta= - 30 to 80 c) paramete r terminal symbol condition min. max. unit address hold time tah8 0 - ns address set up time a0,cs1, cs2 taw8 0 - ns system cycle time tcyc8 300 - ns control ? h ? pulse width (read) tcchr 60 - ns control ? h ? pulse width ( writ e ) tcchw 120 - ns control ? l ? pulse width (read) tcclr 60 - ns control ? l ? pulse width ( writ e ) wr,rd tcclw 60 - ns data set up time tds8 40 - ns data hold time tdh8 15 - ns rd access time tacc8 - 140 ns output disable time d7 ~ d0 toh8 cl=100pf 10 100 ns in p ut signal rising, falling edge cs1,cs2 rw,rd,a0, d7 ~ d0 tr,tf 15 ns (vss=0v, vdd=2.2 to 2.7v, ta= - 30 to 80 c) parameter terminal symbol condition min. max. unit address hold time tah8 0 - ns address set up time a0,cs1, cs2 taw8 0 - ns system cy c le time tcyc8 1000 - ns control ? h ? pulse width (read) tcchr 120 - ns control ? h ? pulse width ( writ e ) tcchw 240 - ns control ? l ? pulse width (read) tcclr 120 - ns control ? l ? pulse width ( writ e ) wr,rd tcclw 120 - ns data set up time tds8 80 - ns data hold time tdh8 30 - ns rd access time tacc8 - 280 ns output disable time d7 ~ d0 toh8 cl=100pf 10 200 ns input signal rising, falling edge cs1,cs2 rw,rd,a0, d7 ~ d0 tr,tf 15 ns note) each timing is specified based on 0.2xvdd and 0.8 xvdd. nju6676 preliminar y read and write characteristics (68 type mpu) (vss=0v, vdd=4.5 to 5.5v, ta= - 30 to 80 c) parameter terminal symbol condition min. max. unit address hold time tah6 0 - ns address set up time taw6 0 - ns sy stem cycle time a0,cs1, cs2 tcyc6 166 - ns enable ? h ? pulse width (read) tcchr 70 - ns enable ? h ? pulse width ( write ) tcchw 30 - ns enable ? l ? pulse width (read) tcclr 30 - ns enable ? l ? pulse width ( write ) e tcclw 30 - ns data set up time tds6 30 - ns data hold time tdh6 10 - ns rd access time tacc6 - 70 ns output disable time d7 ~ d0 toh6 cl=100pf 10 50 ns input signal rising, falling edge e,r/w,a0, d7 ~ d0 tr,tf 15 ns tcyc6 taw6 tew tah6 tdh6 toh6 tds6 tacc6 tr tf e r/w a0,cs1,cs2 d7 to d0 write d7 to d0 read nju6676 preliminar y (vss=0v, vdd=2.7 to 4.5v, ta= - 30 to 80 c) parameter terminal symbol c ondition min. max. unit address hold time tah6 0 - ns address set up time taw6 0 - ns system cycle time a0,cs1, cs2 tcyc6 300 - ns enable ? h ? pulse width (read) tcchr 120 - ns enable ? h ? pulse width ( writ e ) tcchw 60 - ns enable ? l ? pulse wi dth (read) tcclr 60 - ns enable ? l ? pulse width ( writ e ) e tcclw 60 - ns data set up time tds6 40 - ns data hold time tdh6 15 - ns rd access time tacc6 - 140 ns output disable time d7 ~ d0 toh6 cl=100pf 10 100 ns input signal rising, falling e dge e,r/w,a0, d7 ~ d0 tr,tf 15 ns (vss=0v, vdd=2.2 to 2.7v, ta= - 30 to 80 c) parameter terminal symbol condition min. max. unit address hold time tah6 0 - ns address set up time taw6 0 - ns system cycle time a0,cs1, cs2 tcyc6 1000 - ns enable ? h ? pulse width (read) tcchr 240 - ns enable ? h ? pulse width ( writ e ) tcchw 120 - ns enable ? l ? pulse width (read) tcclr 120 - ns enable ? l ? pulse width ( writ e ) e tcclw 120 - ns data set up time tds6 80 - ns data hold time tdh6 30 - n s rd access time tacc6 - 280 ns output disable time d7 ~ d0 toh6 cl=100pf 10 200 ns input signal rising, falling edge e,r/w,a0, d7 ~ d0 tr,tf 15 ns note) each timing is specified based on 0.2xvdd and 0.8xvdd. nju6676 preliminar y write characteristics (serial interface) (vss=0v, vdd=4.5 to 5.5v, ta= - 30 to 80 c) parameter terminal symbol condition min. max. unit serial clock cycle tscyc 200 - ns scl ? h ? pulse width tshw 75 - ns scl ? l ? pulse width scl tslw 75 - ns address set up time t sas 50 - ns address hold time a0 tsah 100 - ns data set up time tsds 50 - ns data hold time si tsdh 50 - ns tcss 100 - ns c s - scl time cs1,cs2 tcsh 100 - ns rising , falling edge scl,a0, cs1,cs2,si tr,tf 15 ns cs1,cs2 a0 scl si tc ss tslw tsah tshw tsdh tsdh tr tf tscyc tcsh tsas nju6676 preliminar y (vss=0v, vdd=2.7 to 4.5v, ta= - 30 to 80 c) parameter terminal symbol condition min. max. unit serial clock cycle tscyc 250 - ns scl ? h ? pulse width tshw 100 - ns scl ? l ? pulse width scl tslw 100 - ns address set up time tsas 150 - ns address hold time a0 tsah 150 - ns da t a set up time tsds 100 - ns data hold time si tsdh 100 - ns tcss 150 - ns c s - scl time cs1,cs2 tcsh 150 - ns rising , falling edge scl,a0, cs1,cs2,si tr,tf 15 ns (vss=0v, vdd=2.2 to 2.7v, ta= - 30 to 80 c) parameter terminal symbol condition mi n. max. unit serial clock cycle tscyc 400 - ns scl ? h ? pulse width tshw 150 - ns scl ? l ? pulse width scl tslw 150 - ns address set up time tsas 250 - ns address hold time a0 tsah 250 - ns data set up time tsds 150 - ns data hold time si ts dh 150 - ns tcss 250 - ns cs - scl time cs1,cs2 tcsh 250 - ns rising , falling edge scl,a0, cs1,cs2,si tr,tf 15 ns note) each timing is specified based on 0.2xvdd and 0.8xvdd. nju6676 preliminar y display control timing characteristics ( v ss =0v, v dd = 4.5 ~ 5.5v, ta= - 30 ~ 80 c) parameter terminal symbol condition min. typ. max. unit fr delay time fr t dfr cl=50pf - 10 40 ns ( v ss =0v, v d d = 2. 7 ~ 4 .5v, ta = - 3 0 ~ 8 0 c) parameter terminal symbol condition min. typ. max. unit fr delay time fr t dfr c l=50pf - 10 80 ns ( v ss =0v, v d d = 2. 2 ~ 2 . 7 v, ta = - 3 0 ~ 8 0 c) parameter terminal symbol condition min. typ. max. unit fr delay time fr t dfr cl=50pf - 50 200 ns note) each timing is specified based on 0.2xvdd and 0.8xvdd. note) the delay time is applied to the master operation only. reset input timing ( v ss =0v, v d d = 4. 5 ~ 5.5v, ta = - 3 0 ~ 8 0 c) parameter terminal symbol condition min. typ. max. unit reset time t r - - 0.5 us reset ? l ? level pulse width res t rw 0.5 - - us ( v ss =0v, v d d = 2. 7 ~ 4 .5v, ta = - 3 0 ~ 8 0 c) parameter terminal symbol condition min. typ. max. unit reset time t r - - 1.0 us reset ? l ? level pulse width res t rw 1.0 - - us ( v ss =0v, v d d = 2. 2 ~ 2 . 7 v, ta = - 3 0 ~ 8 0 c) parameter terminal symbol condition min. typ. max. unit reset time t r - - 1.5 us reset ? l ? level pulse width res t rw 1.5 - - us note) each timing is specified based on 0.2xvdd and 0.8xvdd. cl (out) tdfr fr trw tr res internal circuit status during reset end of reset nju6676 preliminar y n lcd driving waveform s e g 1 s e g 2 s e g 3 s e g 4 1 2 3 4 64 1 2 3 4 5 s e g 0 0 0 65 64 65 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 0 fr v dd v ss v dd v 1 v 2 v 3 v 4 com 0 v 5 v dd v 1 v 2 v 3 v 4 com 1 v 5 v dd v 1 v 2 v 3 v 4 com 2 v 5 v dd v 1 v 2 v 3 v 4 seg 0 v 5 v dd v 1 v 2 v 3 v 4 seg 1 v 5 v dd - v 1 - v 2 - v 3 - v 4 com 0 - seg 0 - v 5 v 5 v 4 v 3 v 2 v 1 v dd - v 1 - v 2 - v 3 - v 4 com 0 - seg 1 - v 5 v 5 v 4 v 3 v 2 v 1 nju6676 preliminar y n application circuit - microprocessor interface example the nju6676 interfaces to 80 type or 68 type mpu direct ly. and the serial interface also communicates with mpu. * : c86 terminal must be fixed vdd or vss. l 80 type mpu l 6 8 type mpu l serial interface mpu a 0 a 0 ~ a7 r es a 0 c s r es r eset c 86 p /s vcc g nd decoder n ju6676 vss v dd i orq r d w r d 0 ~ d7 r d w r d 0 ~ d7 e a 0 vcc a 0 ~ a15 vma r es e r/w d 0 ~ d7 g nd mpu r eset decoder a 0 c s d 0 ~ d7 r es r/w v ss v dd c 86 p /s n ju6676 a 0 vcc a 1 ~ a7 port 1 port 2 r es g nd mpu decoder r eset a 0 c s si scl r es vss v dd c 86 p /s n ju6676 vdd or nju6676 preliminary - 65 x 264 dots driving application circuits example (common and segment drivers extension by using two of nju6676) [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. lcd panel : 65 x 264 m/s fr cl dof m/s fr cl dof nju6676 master nju6676 slave com seg seg com |
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